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An Overview of JTAG for Makers
2026-08-24 | By Maker.io Staff
More complex projects often don’t go strictly as planned, making debugging a necessary step during development. However, even without a bug hunt, designing for testability is a good practice. It allows verifying that designs work as intended and nothing went wrong during assembly. Read on to learn about JTAG and how it can assist makers in testing, programming, and debugging embedded designs.
A Brief Overview of JTAG
JTAG is a standardized, low-level hardware interface for accessing ICs through internal debug and test features defined by the Joint Test Action Group (JTAG) in IEEE 1149.1. These features are implemented in hardware inside compatible ICs, meaning that JTAG debugging, flashing, or testing doesn’t go through the IC’s regular software.
JTAG serves as a serial hardware access protocol that other applications can build upon. The standard defines signals, their characteristics, and certain registers to ensure compatibility. However, actual debugging probes or vendor-specific software are responsible for sending data and interpreting results.
Most important for makers is that JTAG defines five signals that are present on ICs with JTAG features. Those are TCK (Test Clock), TDI and TDO (Test Data In/Out), TMS (Test Mode Select), and an optional TRST (Test Reset) line. The standard further allows daisy-chaining JTAG ICs to facilitate easy testing of an entire board instead of only isolated chips. The TCK, TMS, and TRST lines are common between all devices. However, the TDO of one device is connected to the TDI pin of the next in the chain. Data is then always shifted through the entire chain.
This image illustrates a simple JTAG scan chain, where TDI is shifted serially through each chip (TDO to the next TDI) while TCK and TMS are shared across all devices. Boundary-scan cells at each pin capture or drive signals for testing.
JTAG is a hardware standard that enables multiple functions that help with testing and verifying designs. These include boundary-scan testing, debugging, flashing firmware, and recovering chips stuck in a boot loop or error state.
JTAG Boundary-Scan Testing
JTAG was originally designed as an open, unified boundary-scan testing standard that manufacturers could implement to make it easier for engineers to verify designs without needing different test beds or software for different vendors. This approach proved especially useful when designs became smaller, more complicated, and more integrated, since the entire JTAG hardware is included in each IC. Thus, JTAG testing doesn’t require external probes or exposed pins, which is especially beneficial in packages without exposed pins, such as BGA.
JTAG testing can uncover different issues that can arise during manufacturing, such as open circuits, short circuits, or defective ICs. It does this by testing interconnects and pin states. To facilitate this, each pin of a compliant chip has a so-called boundary-scan cell (BSC) that typically includes a multiplexer and latches. These BSCs allow capturing physical electrical pin states from the pin and, by extension, internal logic, and they can also force electrical signals into the chip through each pin. The data from each pin can then be shifted out as a long stream of binary values via JTAG for further analysis and comparison against the expected values for fault detection.
Multiple compatible ICs can be daisy-chained to form a scan chain (also called a scan path). In that configuration, they can be controlled like a large, continuous shift register, where data passes through each device from its TDI pin out through the TDO and into the TDI of the next IC. Each JTAG device has a unique identifier, which lets analysis tools assign the returned data to the chip in the chain it came from. Certain ICs in the chain can be ignored using a special BYPASS command or by physically altering the board routing. For example, a jumper can be placed between the TDI and TDO of the chip to be skipped.
The main benefit of these multi-chip tests is that developers can verify multiple ICs and their interactions using a single serial connection. However, the process is more fragile and harder to manage than a single-chip approach, since any chip or broken link in the chain can result in failures or errors.
Finding Code Bugs With JTAG Debugging
While originally developed for boundary-scan testing, JTAG is only a hardware protocol that defines signals, voltage levels, registers, and other parameters. This means that it can be applied in different applications, as long as these rules are followed. One such application is debugging, which is probably the best-known use of JTAG in the maker and DIY community.
JTAG debugging uses the same access path as JTAG testing to communicate with microcontrollers on a PCB. However, it serves a different purpose. Instead of uncovering manufacturing or hardware defects, debugging aims to find bugs in software running on an IC. So, instead of enforcing and retrieving physical pin states, a JTAG debugger uses the JTAG protocol to communicate with a built-in debugger on a microcontroller, exposing execution control, register access, memory access, and breakpoint handling.
However, since concrete on-chip debugging implementations often differ between vendors and even architectures, the process relies heavily on an IDE or toolchain to control the data sent and interpret the results. JTAG only acts as the standardized hardware access path into an IC, and it doesn’t implement debugging logic. The toolchain decides what to say, the debugging probe carries the message, and JTAG provides the path into the chip.
Flashing Microcontroller Firmware Using JTAG
Similar to debugging, JTAG can serve as the communication bridge between a toolchain and an on-chip flash memory controller embedded inside a compatible microcontroller. Like in debugging, JTAG acts as the transport layer, and the toolchain or IDE sends different instructions or data to the microcontroller using JTAG to communicate with the chip, instructing it to erase, write, and verify its ROM. The actual programming is handled internally by the microcontroller’s flash controller or programming logic.
Summary
JTAG is a standardized, low-level hardware interface that provides direct access to internal test and debug features of compatible ICs. It defines a set of signals and a serial communication scheme that allows tools to interact with chips during testing, debugging, and programming.
One of its core features is boundary-scan testing, where each pin is connected to a boundary-scan cell that can capture or drive signals. Shifting data through a scan chain makes it possible to detect manufacturing issues such as shorts or open connections across the entire board.
Beyond testing, JTAG is widely used for debugging and flashing firmware. It acts as a transport layer, while the actual logic is implemented in the chip and controlled by external tools. This makes JTAG highly versatile, allowing it to support different use cases across a wide range of devices and development environments.
