The LX2160A chip targets both classical macro cell implementations as well as a higher performance, large centralized deployments. The LX2160A chip natively supports virtualization and NFV. The general purpose cores host 3 GPP upper layer stacks (for example, session control and RRC) as well as proprietary components of the fast path such as L2/schedule, and L2/L3 functions (Ethernet, QoS, IP/IPSec) associated with the S1/X2 interface (base station backhaul). NFVI/VMM networking (such as virtual L2 switching, L2/L3+ traffic filtering, secure overlay L2inL3 networking, L2/L3+ traffic management and traffic filtering) and application components (for example, PDCP) are supported using standardized APIs accessing the accelerators. In order to accommodate the high single-flow IPSEC requirement on the backhaul, the LX2160A chip supports one 25 Gbps elephant flow or three elephant flows of 10 Gbps simultaneously. NXP offers production-proven commercial software for both transport and PDCP.