Latch-up refers to a type of short circuit formed in an integrated circuit and is a parasitic effect generated in the CMOS manufacturing process. The latch-up is produced by the N-P-N-P structure which is formed by the source of the NMOS, the p-substrate, the n-well, and the source of the PMOS. When one of the bipolar junction transistors (BJTs) gets forward-biased, it may form a positive feedback loop bringing up the latch-up effect. When the N-P-N-P structure of the SCR circuit is not triggered, both BJTs stay in the cutoff state. The collector current is made up of the collector-to-base reverse leakage current with very small current gain, and latch-up does not occur at this moment. If some external disturbances appear causing the sudden increase of collector current in one of the BJTs to a certain value, it will feed back to the other one and create the conduction of both BJTs by false-triggering. A low impedance path will be formed between V_DD and GND (V_SS). Due to the positive feedback between these two transistors, an excessive current flow is produced from V_DD to GND which results in the creation of latch-up, even if the external disturbances disappear.